1. Field of the Invention
The invention relates to an architecture for a scan-based integrated circuit (IC). More specifically, the invention relates to a method and circuitry to perform scan compression using a selector operable on a per-shift basis, in multiple modes.
2. Related Art
Testing digital circuits accounts for a significant part of the cost to design, manufacture, and service electronic systems. Scan has long been the fundamental design-for-test (DFT) method to control test costs and aid silicon debug and fault diagnosis, but the number and size of scan test vectors is steadily increasing—even for highly compacted vector sets generated with modern automatic test pattern generation (ATPG).
A scan test pattern is shown by flow 10 in FIG. 1A. In flow 10, step 11 sets up the scan chain configuration using flip-flops in the design, thereby identifying the scan cells of the scan chain. Step 12 shifts the scan-in values into the active scan chains. Step 13 exits the scan configuration. Step 14 applies stimulus to the inputs of the logic to be tested (such as logic 101 in FIG. 1B), and measures the outputs. Step 15 pulses the clocks to capture the logic's response in the flip-flops. Step 16 sets up the scan chain configuration. Step 17 shifts the scan-out values from the active scan chains. Step 18 exits the scan configuration.
Cost-effective test requires a form of scan compression to address the issues of increasingly complex designs, large test pattern sets, and expensive and few automated test equipment (ATE) pads. Of particular interest are on-chip compression/decompression structures that only connect to scan chains and do not require Built-In Self-Test (BIST)-like design changes, such as unknown state (X) avoidance, input/output wrapper cells and improved random testability. Combinational methods are particularly attractive for their simplicity and low overhead in area, timing and design flow.
FIG. 1B illustrates a prior art electronic device which includes a circuit 100 that implements combinational scan compression (CSC). Accordingly, CSC circuit 100 includes a combinational decompressor 110, a combinational compressor 120, and a number of scan chains 101A-101Z coupled between combinational decompressor 110 and combinational compressor 120. Combinational decompressor 110 typically includes a number of multiplexers as shown in FIG. 1C (or exclusive OR gates). Similarly, combinational compressor 120 typically includes a number of exclusive OR gates as illustrated in FIG. 1D. Note that compressors are also called compactors in some prior art literature.
Referring back to FIG. 1B, CSC circuit 100 also includes a logic 101 to implement various features of functionality to be performed by the electronic device. Logic 101 typically includes a number of flip-flops that are required to implement the functionality. A subset of these same flip-flops are used, with multiplexers, to form scan cells that are organized into scan chains of the type shown in FIG. 1B. Specifically, flip-flops 101A1F and 101APF illustrated in FIG. 1E are portions of logic 101 that are made accessible via an external interface formed by input terminals 111A-111N, 112 and output terminals 121A-121Q of the electronic device, by use of multiplexers 101A1M and 101APM. Each corresponding pair, constituting a multiplexer driving a flip flop, forms a scan cell as shown in FIG. 1E.
Note that the primary input terminals 102PI and the primary output terminals 102PO of the logic 101 are physically identical to above-described input terminals 111A-111N, 112 and output terminals 121A-121Q of the external interface, but are shown separately in FIG. 1B to clearly show a distinction between scan mode operation and normal functional operation of CSC circuit 100. The difference between the two modes of operation is identified to CSC circuit 100 from an external source, via a scan enable signal on input terminal 112.
In FIG. 1A's step 11, using a scan_enable (i.e. a control) signal, multiplexers 101A1M and 101APM can be configured to allow scan-in values to be shifted into flip-flops 101A1F and 101APF without going through logic 101 in step 102. In step 103, multiplexers 101A1M and 101APM can be reconfigured to accept values from logic 101. At this point, stimulus can be applied to CSC circuit 100 in step 104. A pulse can be applied to the clock CLK terminals of flip-flops 101A1F and 101APF to capture the resulting values in step 105. In step 106, multiplexers 101A1M and 101APM can be reconfigured to shift those resulting values out through the scan chain comprising flip-flops 123. Step 108 marks the end of processing a single scan test pattern.
Scan load compression techniques exploit the low density of care bits in scan load data. Several combinational load compression methods have been proposed, including: ATE-based run-length encoding, ATE-independent shared scan-in “Illinois Scan”, XOR-based expander networks inserted between scan input pins and internal scan chains, and MUX-based load decompressors. Scan unload compression techniques exploit the fact that error values appear more or less randomly, and only on a few scan chains at a time.
One issue with use of scan unload compression arises in the presence of unknown values (X) values. In “pure” scan designs which do not use any compression, presence of unknown values is normally handled by a tester which receives all values at output terminals 121A-121Q. The tester used with non-compression scan designs can be configured to ignore the unknown (X) values, and focus on evaluating non-X values. The location of the X values is typically known to an ATPG device which creates and loads test patterns into the tester. Specifically, the ATPG device configures the tester appropriately, on a scan chain by scan chain basis, and within each scan chain, on a scan cell by scan cell basis. However, in scan designs which use compression (or compaction) of some kind, an X value can be combined or otherwise mixed with one or more non-X values, by compressor 120 in a process called X-masking, which prevents tester 130 (FIG. 1B) from evaluating non-X values of interest.
Designs of scan compression in such presence of unknowns (Xs) may use circuitry to mask selected unload values so that Xs do not reach the unload compressor, or may selectively unload a subset of scan chains and mask unknown values at the tester. However, recent designs can often have more than two Xs per shift which exceeds the X-tolerance that can be ensured by the method of FIG. 1B. Several factors can contribute to increase the number of Xs per shift: (1) Increased functional complexity of recent designs results in extended usage of RAMs, which are X-sources for basic-scan ATPG. Area and performance considerations often prevent adding DFT structures to block the Xs from propagating to scan cells, thus the overall number of Xs increases. (2) Aggressive timing of designs creates a large number of false paths that are modeled by X-ing out the values captured in scan cells during test application, thus also increasing the number of Xs. (3) Higher compressions require increased number of internal scan chains, thus increasing the number of Xs per shift even if the total number of Xs remained unchanged. (4) Test cost reduction drives the number of available ATE pins down, either by using low-cost testers, or by employing multi-site testing. Fewer pins implies fewer X's per shift can be tolerated by a combinational compactor before loss of observability occurs.
Several designs of scan compression in presence of unknowns (Xs) are described in U.S. Pat. No. 6,829,740. Specifically, U.S. Pat. No. 6,829,740 granted to Rajski et al and entitled “Method and Apparatus for Selectively Compacting Test Responses” is incorporated by reference herein, in its entirety, as background. This patent discloses a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments disclosed by Rajski in this patent allow selective masking of a variable number of scan chain outputs.
Rajski's technique as described in U.S. Pat. No. 6,829,740 appears to be to block unknowns (Xs). The current inventors note that in such a technique, information about the precise location of all Xs needs to be transmitted from the ATPG device to the selector and/or compactor, but in doing so if the volume of information becomes large, the advantage of performing scan compression itself becomes annihilated. Additionally, the current inventors note that in blocking out all Xs, some non-X values may also be blocked which can be problematic if some of the non-X values happen to be data that needs to be observed.
Rajski also describes a class of finite memory compactors called “convolution compactors” designed specifically for Embedded Deterministic Test (EDT) in an article entitled “Convolution Compaction of Test Responses” by Janusz Rajski, Jerzy Tyszer, Chen Wang and Sudhakar M. Reddy, ITC International Test Conference, 2003, pp 745-754. This article is incorporated by reference herein in its entirety, as background. An example in Rajski's paper uses limited memory and lacks feedback, because of which the convolution compactors are capable of handling some number of X states. Rajski states that a single error from one scan cell is detected on the compactor outputs in the presence of a single X-state produced by another scan cell. Rajski further states that if multiple X states occur, the error propagation paths can be blocked and the error may not be observed at all.
The current inventors note that Rajski's above-described paper also appears to require information about the location of Xs to be transmitted from the ATPG device to the selector and/or compactor, which has several disadvantages as noted above.
In contrast to Rajski's techniques, an X-tolerant deterministic BIST architecture (called XDBIST) is described in an article by P. Wohl, J. Waicukauski, S. Patel and M. Amin entitled “X-Tolerant Compression and Application of Scan ATPG patterns in a BIST architecture,” Proc. of International TestConference, pp. 727-736, 2003, which is incorporated by reference herein in its entirety. As stated in this article, XDBIST can tolerate any number of X's propagating to the scan chains, with no degradation in compression or application efficiency. Specifically, this article teaches reducing scan-out data by selectively observing only the desired scan chains by use of an observe selector. Chain selection is controlled by a separate selector register.
However, XDBIST requires sequentially loading X-avoiding data with every load. Accordingly, the current inventors note that both XDBIST and Rajski's technique suffer from the complexity and overhead of sequential elements. Also, both are limited to only one X-avoiding data selection per load, whereas the profile of Xs changes with every shift cycle of the load. Therefore, the current inventors believe that the selection of non-X data is too coarse, which can result in lower test quality and higher pattern count, i.e., lower compression. Finally, XDBIST allows only a fraction of the scan chains to be observed during each unload, which can also result in lower test quality and higher pattern count, i.e., lower compression.
Additionally, another BIST architecture for filtering X values output by scan chains is disclosed in U.S. Pat. No. 6,993,694 which is incorporated by reference herein in its entirety. The method described in this patent requires all X's to be eliminated before data can be compressed in a MISR. Depending on the tradeoff taken this can result in too much X-avoiding data, or too much masking of non-X data. In either case, the advantages of compression can be annihilated by the increased pattern count and data volume.